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UVM Template Generator

by svf-tg — last modified 2010-06-15 03:01

This page runs the svfTG and returns a gzipped tar file containing the appropriate directory structure.

Name of the project : Please choose a name that is a valid identifier(no spaces, semicolons etc)
Enter the name of the testbench. Multiple testbenches can be specified by entering one testbench name per line.

UVC (Verification IP)

Please enter 1 entry per line.

Syntax:

    uvc_name [numInst=n][numMasters=n] [numSlaves=n] [hasBusMonitor=0,1] [agentIsTop=0,1]

Where

      uvc_name - Identifier specifying the name of the uvc class
      numInst=n- Number instances for this UVC (default is 1)
      numMaster=n- Number of master agents in this UVC (default is 1)
      numSlaves=n- Number of slave agents in this UVC (default is 1)
      hasBusMonitor=0,1- Controls if this UVC includes a Bus Monitor (default is 0)
      agentIsTop=0,1- Agent is top level component (default is 0)

Example:

The following generates 4 instances of pwr_pi class, each with 1 master & 3 slave agents: pwr_pi numInst=4 numMasters=2

Specify a test group on a line followed by a list of tests all separated by spaces. i.e. group_a test1 test2 ... testn

We appreciate your feedback. Please email svf-tg@paradigm-works.com.


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